eSilicon Brings Virtualization to Online Portal
MADISON, Wis. — An IC designers’ job is mired in “what if’s.” Depending on choices among of metal stacksMultiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR.Multiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR., process flavors, or types of memory architecture, a new design could result in a chip dramatically different in power, performance and area.
In theory, running a number of trial implementation could help designers to arrive at better decisions. Yet, when design options for SoCs are so large, costs and time penalties are too huge to make a trial-and-error process practical.
eSilicon Corporation, a design service company for semiconductor designs and manufacturing, wants to make the ASIC designer’s decision process as painless as possible. eSilicon is unveiling Tuesday (May 19) a new tool called “Optimizer.”
With this tool, the company promises ASIC designers “an easy way to access eSilicon’s block- and chip-level optimization services.”
The Optimizer will be a part of eSilicon’s revamped, second-generation online platform. Since last year, eSilicon has been a trailblazer among design service companies in the brave new world of web-based design service tools.
eSilicon’s Navigator has allowed designers to search and select eSilicon IP online, encouraging them, for example, to tinker with, build and generate a complete memory subsystem before making a purchase decision.
eSilicon also offers a Web-based tool called Explorer. It helps designers evaluate options and get fast, accurate quotes for Multi-project Wafer (MPW) and GDSII handoffs.
Another eSilicon tool, called Tracker, literally allows IC designers to see design progress real-time and track IC delivery.
These three tools — Navigator, Explorer and Tracker — used to be on separate online platforms that required users to use separate log-ins. But now, along with the new Optimizer, four tools are unified into the single online ASIC design and manufacturing platform, according to Mike Gianfagna, eSilicon’s vice president of marketing.
Unlike Navigator, Explorer and Tracker, Optimizer doesn’t exactly offer IC designers a lot of knobs and dials to tune so that they can optimize designs on their own.
Instead, users must first download free software that will analyze their design’s register transfer language (RTL) description to check for robustness.
“If RTL is well structured, you get the green light,” explained Gianfagna. Users can then request a design optimization service engagement online, he noted.
Leveraging its unique design virtualization technology, eSilicon is promising to find for its customers the optimal design implementation from a power, performance or area perspective. The service is built on a “pay for results” philosophy. The customer pays for the service only if a pre-determined optimization result is achieved, the company explained.
Assume, for example, that you’veVolumetric Efficiency designed a chip on your own without signing up as eSilicon’s client, said Gianfagna. By using Optimizer online, “you now have a way to evaluate your chip – in terms of power, performance and area — and get valuable feedback from us.” The bottom line: eSilicon is “making Optimizer available for anybody,” he said.