Silicon Labs enables clock-tree-on-a-chip
Silicon Labs claims best-in-class jitter performance for its Si5348 clock IC which enables hardware designers to implement a “clock-tree-on-a-chip” solution for Synchronous Ethernet (SyncE), IEEE 1588v2 and general-purpose frequency translation for wireless and telecom infrastructure, broadband networks (e.g., G.fast DSL and PON) and data centre applications.
SyncE and IEEE 1588 have become increasingly popular methods to deliver synchronization over packet networks. As these technologies become more widespread, networking equipment designers are demanding more flexible, cost-effective timing solutions that easily integrate into existing hardware architectures. Conventional network synchronizer clocks rely on rigid synchronization clock chip architectures that borrow heavily from legacy Stratum 3 clock ICs, which are not optimized for size, power or performance.
The Si5348 clock delivers a solution that claims to be 50% smaller, 35% lower power and 80% lower jitter than conventional synchronizers delivering a timing solution compliant with IEEE 1588, SyncE and Stratum 3 clocking requirements, enabling the device to be used in a wide variety of timing card and line card clock architectures. The Si5348 clock has been designed to interoperate with IEEE 1588 software running on an external host processor, further simplifying system integration.
In packet timing applications, high-stability oscillators play a critical role in defining the network’s overall performance in terms of frequency, time and phase accuracy. Network topologies often will dictate the type of temperature-controlled crystal oscillator (TCXO) or oven-controlled crystal oscillator (OCXO) required at each node in the network. The Si5348 clock supports a universal reference input port, enabling the device to be paired with any frequency TCXO/OCXO.