TI Obsoletes FPGA
PORTLAND, Ore. — Texas Instruments (TI) — king of the DSP — is at it again, this time targeting the FPGA market with a 9 processor jack-of-all-trades device capable of radically downsizing mammoth avionic, military, testtest is test and measurement and medical instruments — from backpack radars to portable magnetic resonance instruments (MRIs).
According to TI, the Keystone-II (66AK2L06) solution allows devices using it to be 66 percent smaller, consume 60 percent less power, cost 50 percent less and are 3-times faster to market than using an FPGA solution.
“Our newest Keystone II system-on-chip [SoC] has two ARM’s Cortex A15 MPCore processors, four 1.2 GHz C66x DSPs [digital signal processors) and four programmable accelerators,” Robert Ferguson, communications processors business development manager at TI told EE Times.
TI’s FPGA-killer is an SoC with two ARM cores, four DSPs and four programmable hardware accelerators all connected by TeraNet on-chip and by four lanes of 7.8-Gbit JESD204B interfaces off-chip.
That spells significant system-level savings for high-speed data acquisition when paired with 4-lanes of JEDEC-compatible input/output (I/O) running at 7.3 Gbits/sec per lane (JESD204B).
The four on-chip accelerators are connected to the other six cores, and each other, with TI’s on-chip TeraNet. The four accelerators include a programmable digital-radio front-end (DFE), two programmable Fast Fourier Transform coprocessors (FFTCs), a programmable security accelerator for high-speed encryption/decryption and a packet accelerator for network coprocessor (NETCP) for operations like header matching, and packet modification operations, connected to four gigabit Ethernet (GbE) modules to send and receive packets.