Yole: Flip Chip Investment Reboots in 2018
Due to the growth of the semiconductor business, the wider adoption of Cu pillar solutions and the introduction of flip chip technology for LED and CMOS image sensors (CIS) applications, the flip chip market is expanding.
However, market research firm Yole Développement (Yole) expects flip chip capacity will max out by 2017, requiring new investment in the technology by 2018.
“Flip chip assembly technology provides various benefits such as high I/O counts, fine pitch interconnection, and superior electrical and thermal performance,” explains Thibault Buisson, technology and market analyst, advanced packaging at Yole. “This drives its application across specific segments.”The maximum growth in flip-chip bumping capacity will come from Cu pillars, driven by the finer pitches, higher I/O counts, lithography nodes below 28nm, emergence of 2.5D/3D packaging, increased current densityA figure of merit usually expressed in Joules per cubic inch for capacitors and thermal dissipation needs. In the meantime lead-free solder bumping is expected to grow at just 2 percent CAGR as outsourced semiconductor assembly and testtest is test (OSATs) companies and foundries convert their existing solder bumping lines to Cu pillar lines. With the scaling of the flip chip pitch, OSATs are presently pushing the envelope of C2 mass reflow bonding with capillary underfill to pitches as low as 50µm by formulating engineered materials and improving assembly processes. However, if the pitch reaches or falls below 40µm thermo compression bonding (TCB) will be the key option because of its high placement accuracy.